001 // Copyright (c) National Instruments 2009. All Rights Reserved.
002 // Do Not Edit... this file is generated!
003
004 package edu.wpi.first.wpilibj.fpga;
005
006 import com.ni.rio.*;
007
008 public class tCounter extends tSystem
009 {
010
011 public tCounter(final int sys_index)
012 {
013 super();
014 m_SystemIndex = sys_index;
015 if (status.isNotFatal() && m_SystemIndex >= kNumSystems)
016 {
017 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
018 }
019
020 }
021
022 protected void finalize()
023 {
024 super.finalize();
025 }
026
027 public int getSystemIndex()
028 {
029 return m_SystemIndex;
030 }
031
032 public static final int kNumSystems = 8;
033 public final int m_SystemIndex;
034
035
036
037
038
039
040
041
042 //////////////////////////////////////////////////////////////////////////////////////////////////
043 // Accessors for Output
044 //////////////////////////////////////////////////////////////////////////////////////////////////
045 private static final int kOutput_Direction_BitfieldMask = 0x80000000;
046 private static final int kOutput_Direction_BitfieldOffset = 31;
047 private static final int kOutput_Value_BitfieldMask = 0x7FFFFFFF;
048 private static final int kOutput_Value_BitfieldOffset = 0;
049 private static final int kCounter0_Output_Address = 0x82E8;
050 private static final int kCounter1_Output_Address = 0x82FC;
051 private static final int kCounter2_Output_Address = 0x8310;
052 private static final int kCounter3_Output_Address = 0x8324;
053 private static final int kCounter4_Output_Address = 0x8338;
054 private static final int kCounter5_Output_Address = 0x834C;
055 private static final int kCounter6_Output_Address = 0x8360;
056 private static final int kCounter7_Output_Address = 0x8374;
057 private static final int kOutput_Addresses [] =
058 {
059 kCounter0_Output_Address,
060 kCounter1_Output_Address,
061 kCounter2_Output_Address,
062 kCounter3_Output_Address,
063 kCounter4_Output_Address,
064 kCounter5_Output_Address,
065 kCounter6_Output_Address,
066 kCounter7_Output_Address,
067 };
068
069 public int readOutput()
070 {
071
072 int result = NiFpga.readU32(m_DeviceHandle, kOutput_Addresses[m_SystemIndex], status);
073 int regValue = result ;
074 return (int)(regValue);
075 }
076 public boolean readOutput_Direction()
077 {
078
079 int result = NiFpga.readU32(m_DeviceHandle, kOutput_Addresses[m_SystemIndex], status);
080 int regValue = result ;
081 int bitfieldValue = ((regValue & kOutput_Direction_BitfieldMask) >>> kOutput_Direction_BitfieldOffset);
082 return ((bitfieldValue) != 0 ? true : false);
083 }
084 public int readOutput_Value()
085 {
086
087 int result = NiFpga.readU32(m_DeviceHandle, kOutput_Addresses[m_SystemIndex], status);
088 int regValue = result ;
089 int bitfieldValue = ((regValue & kOutput_Value_BitfieldMask) >>> kOutput_Value_BitfieldOffset);
090 // Sign extension
091 bitfieldValue <<= 1;
092 bitfieldValue >>= 1;
093 return (int)(bitfieldValue);
094 }
095
096 //////////////////////////////////////////////////////////////////////////////////////////////////
097 // Accessors for Config
098 //////////////////////////////////////////////////////////////////////////////////////////////////
099 private static final int kConfig_UpSource_Channel_BitfieldMask = 0xF0000000;
100 private static final int kConfig_UpSource_Channel_BitfieldOffset = 28;
101 private static final int kConfig_UpSource_Module_BitfieldMask = 0x08000000;
102 private static final int kConfig_UpSource_Module_BitfieldOffset = 27;
103 private static final int kConfig_UpSource_AnalogTrigger_BitfieldMask = 0x04000000;
104 private static final int kConfig_UpSource_AnalogTrigger_BitfieldOffset = 26;
105 private static final int kConfig_DownSource_Channel_BitfieldMask = 0x03C00000;
106 private static final int kConfig_DownSource_Channel_BitfieldOffset = 22;
107 private static final int kConfig_DownSource_Module_BitfieldMask = 0x00200000;
108 private static final int kConfig_DownSource_Module_BitfieldOffset = 21;
109 private static final int kConfig_DownSource_AnalogTrigger_BitfieldMask = 0x00100000;
110 private static final int kConfig_DownSource_AnalogTrigger_BitfieldOffset = 20;
111 private static final int kConfig_IndexSource_Channel_BitfieldMask = 0x000F0000;
112 private static final int kConfig_IndexSource_Channel_BitfieldOffset = 16;
113 private static final int kConfig_IndexSource_Module_BitfieldMask = 0x00008000;
114 private static final int kConfig_IndexSource_Module_BitfieldOffset = 15;
115 private static final int kConfig_IndexSource_AnalogTrigger_BitfieldMask = 0x00004000;
116 private static final int kConfig_IndexSource_AnalogTrigger_BitfieldOffset = 14;
117 private static final int kConfig_IndexActiveHigh_BitfieldMask = 0x00002000;
118 private static final int kConfig_IndexActiveHigh_BitfieldOffset = 13;
119 private static final int kConfig_UpRisingEdge_BitfieldMask = 0x00001000;
120 private static final int kConfig_UpRisingEdge_BitfieldOffset = 12;
121 private static final int kConfig_UpFallingEdge_BitfieldMask = 0x00000800;
122 private static final int kConfig_UpFallingEdge_BitfieldOffset = 11;
123 private static final int kConfig_DownRisingEdge_BitfieldMask = 0x00000400;
124 private static final int kConfig_DownRisingEdge_BitfieldOffset = 10;
125 private static final int kConfig_DownFallingEdge_BitfieldMask = 0x00000200;
126 private static final int kConfig_DownFallingEdge_BitfieldOffset = 9;
127 private static final int kConfig_Mode_BitfieldMask = 0x00000180;
128 private static final int kConfig_Mode_BitfieldOffset = 7;
129 private static final int kConfig_PulseLengthThreshold_BitfieldMask = 0x0000007E;
130 private static final int kConfig_PulseLengthThreshold_BitfieldOffset = 1;
131 private static final int kConfig_PulseLengthThreshold_FixedPointIntegerShift = 8;
132 private static final int kConfig_Enable_BitfieldMask = 0x00000001;
133 private static final int kConfig_Enable_BitfieldOffset = 0;
134 private static final int kCounter0_Config_Address = 0x82E0;
135 private static final int kCounter1_Config_Address = 0x82F4;
136 private static final int kCounter2_Config_Address = 0x8308;
137 private static final int kCounter3_Config_Address = 0x831C;
138 private static final int kCounter4_Config_Address = 0x8330;
139 private static final int kCounter5_Config_Address = 0x8344;
140 private static final int kCounter6_Config_Address = 0x8358;
141 private static final int kCounter7_Config_Address = 0x836C;
142 private static final int kConfig_Addresses [] =
143 {
144 kCounter0_Config_Address,
145 kCounter1_Config_Address,
146 kCounter2_Config_Address,
147 kCounter3_Config_Address,
148 kCounter4_Config_Address,
149 kCounter5_Config_Address,
150 kCounter6_Config_Address,
151 kCounter7_Config_Address,
152 };
153
154 public void writeConfig(final int value)
155 {
156
157 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], value, status);
158 }
159 public void writeConfig_UpSource_Channel(final int value)
160 {
161
162 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
163 regValue &= ~kConfig_UpSource_Channel_BitfieldMask;
164 regValue |= ((value) << kConfig_UpSource_Channel_BitfieldOffset) & kConfig_UpSource_Channel_BitfieldMask;
165 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
166 }
167 public void writeConfig_UpSource_Module(final int value)
168 {
169
170 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
171 regValue &= ~kConfig_UpSource_Module_BitfieldMask;
172 regValue |= ((value) << kConfig_UpSource_Module_BitfieldOffset) & kConfig_UpSource_Module_BitfieldMask;
173 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
174 }
175 public void writeConfig_UpSource_AnalogTrigger(final boolean value)
176 {
177
178 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
179 regValue &= ~kConfig_UpSource_AnalogTrigger_BitfieldMask;
180 regValue |= (((value ? 1 : 0)) << kConfig_UpSource_AnalogTrigger_BitfieldOffset) & kConfig_UpSource_AnalogTrigger_BitfieldMask;
181 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
182 }
183 public void writeConfig_DownSource_Channel(final int value)
184 {
185
186 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
187 regValue &= ~kConfig_DownSource_Channel_BitfieldMask;
188 regValue |= ((value) << kConfig_DownSource_Channel_BitfieldOffset) & kConfig_DownSource_Channel_BitfieldMask;
189 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
190 }
191 public void writeConfig_DownSource_Module(final int value)
192 {
193
194 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
195 regValue &= ~kConfig_DownSource_Module_BitfieldMask;
196 regValue |= ((value) << kConfig_DownSource_Module_BitfieldOffset) & kConfig_DownSource_Module_BitfieldMask;
197 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
198 }
199 public void writeConfig_DownSource_AnalogTrigger(final boolean value)
200 {
201
202 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
203 regValue &= ~kConfig_DownSource_AnalogTrigger_BitfieldMask;
204 regValue |= (((value ? 1 : 0)) << kConfig_DownSource_AnalogTrigger_BitfieldOffset) & kConfig_DownSource_AnalogTrigger_BitfieldMask;
205 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
206 }
207 public void writeConfig_IndexSource_Channel(final int value)
208 {
209
210 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
211 regValue &= ~kConfig_IndexSource_Channel_BitfieldMask;
212 regValue |= ((value) << kConfig_IndexSource_Channel_BitfieldOffset) & kConfig_IndexSource_Channel_BitfieldMask;
213 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
214 }
215 public void writeConfig_IndexSource_Module(final int value)
216 {
217
218 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
219 regValue &= ~kConfig_IndexSource_Module_BitfieldMask;
220 regValue |= ((value) << kConfig_IndexSource_Module_BitfieldOffset) & kConfig_IndexSource_Module_BitfieldMask;
221 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
222 }
223 public void writeConfig_IndexSource_AnalogTrigger(final boolean value)
224 {
225
226 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
227 regValue &= ~kConfig_IndexSource_AnalogTrigger_BitfieldMask;
228 regValue |= (((value ? 1 : 0)) << kConfig_IndexSource_AnalogTrigger_BitfieldOffset) & kConfig_IndexSource_AnalogTrigger_BitfieldMask;
229 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
230 }
231 public void writeConfig_IndexActiveHigh(final boolean value)
232 {
233
234 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
235 regValue &= ~kConfig_IndexActiveHigh_BitfieldMask;
236 regValue |= (((value ? 1 : 0)) << kConfig_IndexActiveHigh_BitfieldOffset) & kConfig_IndexActiveHigh_BitfieldMask;
237 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
238 }
239 public void writeConfig_UpRisingEdge(final boolean value)
240 {
241
242 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
243 regValue &= ~kConfig_UpRisingEdge_BitfieldMask;
244 regValue |= (((value ? 1 : 0)) << kConfig_UpRisingEdge_BitfieldOffset) & kConfig_UpRisingEdge_BitfieldMask;
245 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
246 }
247 public void writeConfig_UpFallingEdge(final boolean value)
248 {
249
250 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
251 regValue &= ~kConfig_UpFallingEdge_BitfieldMask;
252 regValue |= (((value ? 1 : 0)) << kConfig_UpFallingEdge_BitfieldOffset) & kConfig_UpFallingEdge_BitfieldMask;
253 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
254 }
255 public void writeConfig_DownRisingEdge(final boolean value)
256 {
257
258 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
259 regValue &= ~kConfig_DownRisingEdge_BitfieldMask;
260 regValue |= (((value ? 1 : 0)) << kConfig_DownRisingEdge_BitfieldOffset) & kConfig_DownRisingEdge_BitfieldMask;
261 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
262 }
263 public void writeConfig_DownFallingEdge(final boolean value)
264 {
265
266 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
267 regValue &= ~kConfig_DownFallingEdge_BitfieldMask;
268 regValue |= (((value ? 1 : 0)) << kConfig_DownFallingEdge_BitfieldOffset) & kConfig_DownFallingEdge_BitfieldMask;
269 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
270 }
271 public void writeConfig_Mode(final int value)
272 {
273
274 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
275 regValue &= ~kConfig_Mode_BitfieldMask;
276 regValue |= ((value) << kConfig_Mode_BitfieldOffset) & kConfig_Mode_BitfieldMask;
277 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
278 }
279 public void writeConfig_PulseLengthThreshold(final int value)
280 {
281
282 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
283 regValue &= ~kConfig_PulseLengthThreshold_BitfieldMask;
284 regValue |= ((value >>> kConfig_PulseLengthThreshold_FixedPointIntegerShift) << kConfig_PulseLengthThreshold_BitfieldOffset) & kConfig_PulseLengthThreshold_BitfieldMask;
285 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
286 }
287 public void writeConfig_Enable(final boolean value)
288 {
289
290 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
291 regValue &= ~kConfig_Enable_BitfieldMask;
292 regValue |= (((value ? 1 : 0)) << kConfig_Enable_BitfieldOffset) & kConfig_Enable_BitfieldMask;
293 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
294 }
295 public int readConfig()
296 {
297
298 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
299 int regValue = result ;
300 return (int)(regValue);
301 }
302 public byte readConfig_UpSource_Channel()
303 {
304
305 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
306 int regValue = result ;
307 int bitfieldValue = ((regValue & kConfig_UpSource_Channel_BitfieldMask) >>> kConfig_UpSource_Channel_BitfieldOffset);
308 return (byte)((bitfieldValue) & 0x0000000F);
309 }
310 public byte readConfig_UpSource_Module()
311 {
312
313 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
314 int regValue = result ;
315 int bitfieldValue = ((regValue & kConfig_UpSource_Module_BitfieldMask) >>> kConfig_UpSource_Module_BitfieldOffset);
316 return (byte)((bitfieldValue) & 0x00000001);
317 }
318 public boolean readConfig_UpSource_AnalogTrigger()
319 {
320
321 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
322 int regValue = result ;
323 int bitfieldValue = ((regValue & kConfig_UpSource_AnalogTrigger_BitfieldMask) >>> kConfig_UpSource_AnalogTrigger_BitfieldOffset);
324 return ((bitfieldValue) != 0 ? true : false);
325 }
326 public byte readConfig_DownSource_Channel()
327 {
328
329 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
330 int regValue = result ;
331 int bitfieldValue = ((regValue & kConfig_DownSource_Channel_BitfieldMask) >>> kConfig_DownSource_Channel_BitfieldOffset);
332 return (byte)((bitfieldValue) & 0x0000000F);
333 }
334 public byte readConfig_DownSource_Module()
335 {
336
337 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
338 int regValue = result ;
339 int bitfieldValue = ((regValue & kConfig_DownSource_Module_BitfieldMask) >>> kConfig_DownSource_Module_BitfieldOffset);
340 return (byte)((bitfieldValue) & 0x00000001);
341 }
342 public boolean readConfig_DownSource_AnalogTrigger()
343 {
344
345 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
346 int regValue = result ;
347 int bitfieldValue = ((regValue & kConfig_DownSource_AnalogTrigger_BitfieldMask) >>> kConfig_DownSource_AnalogTrigger_BitfieldOffset);
348 return ((bitfieldValue) != 0 ? true : false);
349 }
350 public byte readConfig_IndexSource_Channel()
351 {
352
353 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
354 int regValue = result ;
355 int bitfieldValue = ((regValue & kConfig_IndexSource_Channel_BitfieldMask) >>> kConfig_IndexSource_Channel_BitfieldOffset);
356 return (byte)((bitfieldValue) & 0x0000000F);
357 }
358 public byte readConfig_IndexSource_Module()
359 {
360
361 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
362 int regValue = result ;
363 int bitfieldValue = ((regValue & kConfig_IndexSource_Module_BitfieldMask) >>> kConfig_IndexSource_Module_BitfieldOffset);
364 return (byte)((bitfieldValue) & 0x00000001);
365 }
366 public boolean readConfig_IndexSource_AnalogTrigger()
367 {
368
369 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
370 int regValue = result ;
371 int bitfieldValue = ((regValue & kConfig_IndexSource_AnalogTrigger_BitfieldMask) >>> kConfig_IndexSource_AnalogTrigger_BitfieldOffset);
372 return ((bitfieldValue) != 0 ? true : false);
373 }
374 public boolean readConfig_IndexActiveHigh()
375 {
376
377 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
378 int regValue = result ;
379 int bitfieldValue = ((regValue & kConfig_IndexActiveHigh_BitfieldMask) >>> kConfig_IndexActiveHigh_BitfieldOffset);
380 return ((bitfieldValue) != 0 ? true : false);
381 }
382 public boolean readConfig_UpRisingEdge()
383 {
384
385 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
386 int regValue = result ;
387 int bitfieldValue = ((regValue & kConfig_UpRisingEdge_BitfieldMask) >>> kConfig_UpRisingEdge_BitfieldOffset);
388 return ((bitfieldValue) != 0 ? true : false);
389 }
390 public boolean readConfig_UpFallingEdge()
391 {
392
393 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
394 int regValue = result ;
395 int bitfieldValue = ((regValue & kConfig_UpFallingEdge_BitfieldMask) >>> kConfig_UpFallingEdge_BitfieldOffset);
396 return ((bitfieldValue) != 0 ? true : false);
397 }
398 public boolean readConfig_DownRisingEdge()
399 {
400
401 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
402 int regValue = result ;
403 int bitfieldValue = ((regValue & kConfig_DownRisingEdge_BitfieldMask) >>> kConfig_DownRisingEdge_BitfieldOffset);
404 return ((bitfieldValue) != 0 ? true : false);
405 }
406 public boolean readConfig_DownFallingEdge()
407 {
408
409 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
410 int regValue = result ;
411 int bitfieldValue = ((regValue & kConfig_DownFallingEdge_BitfieldMask) >>> kConfig_DownFallingEdge_BitfieldOffset);
412 return ((bitfieldValue) != 0 ? true : false);
413 }
414 public byte readConfig_Mode()
415 {
416
417 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
418 int regValue = result ;
419 int bitfieldValue = ((regValue & kConfig_Mode_BitfieldMask) >>> kConfig_Mode_BitfieldOffset);
420 return (byte)((bitfieldValue) & 0x00000003);
421 }
422 public short readConfig_PulseLengthThreshold()
423 {
424
425 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
426 int regValue = result ;
427 int bitfieldValue = ((regValue & kConfig_PulseLengthThreshold_BitfieldMask) >>> kConfig_PulseLengthThreshold_BitfieldOffset) << kConfig_PulseLengthThreshold_FixedPointIntegerShift;
428 return (short)((bitfieldValue) & 0x00003FFF);
429 }
430 public boolean readConfig_Enable()
431 {
432
433 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
434 int regValue = result ;
435 int bitfieldValue = ((regValue & kConfig_Enable_BitfieldMask) >>> kConfig_Enable_BitfieldOffset);
436 return ((bitfieldValue) != 0 ? true : false);
437 }
438
439 //////////////////////////////////////////////////////////////////////////////////////////////////
440 // Accessors for TimerOutput
441 //////////////////////////////////////////////////////////////////////////////////////////////////
442 private static final int kTimerOutput_Period_BitfieldMask = 0xFFFFFE00;
443 private static final int kTimerOutput_Period_BitfieldOffset = 9;
444 private static final int kTimerOutput_Period_FixedPointIntegerShift = 1;
445 private static final int kTimerOutput_Count_BitfieldMask = 0x000001FE;
446 private static final int kTimerOutput_Count_BitfieldOffset = 1;
447 private static final int kTimerOutput_Stalled_BitfieldMask = 0x00000001;
448 private static final int kTimerOutput_Stalled_BitfieldOffset = 0;
449 private static final int kCounter0_TimerOutput_Address = 0x82F0;
450 private static final int kCounter1_TimerOutput_Address = 0x8304;
451 private static final int kCounter2_TimerOutput_Address = 0x8318;
452 private static final int kCounter3_TimerOutput_Address = 0x832C;
453 private static final int kCounter4_TimerOutput_Address = 0x8340;
454 private static final int kCounter5_TimerOutput_Address = 0x8354;
455 private static final int kCounter6_TimerOutput_Address = 0x8368;
456 private static final int kCounter7_TimerOutput_Address = 0x837C;
457 private static final int kTimerOutput_Addresses [] =
458 {
459 kCounter0_TimerOutput_Address,
460 kCounter1_TimerOutput_Address,
461 kCounter2_TimerOutput_Address,
462 kCounter3_TimerOutput_Address,
463 kCounter4_TimerOutput_Address,
464 kCounter5_TimerOutput_Address,
465 kCounter6_TimerOutput_Address,
466 kCounter7_TimerOutput_Address,
467 };
468
469 public int readTimerOutput()
470 {
471
472 int result = NiFpga.readU32(m_DeviceHandle, kTimerOutput_Addresses[m_SystemIndex], status);
473 int regValue = result ;
474 return (int)(regValue);
475 }
476 public int readTimerOutput_Period()
477 {
478
479 int result = NiFpga.readU32(m_DeviceHandle, kTimerOutput_Addresses[m_SystemIndex], status);
480 int regValue = result ;
481 int bitfieldValue = ((regValue & kTimerOutput_Period_BitfieldMask) >>> kTimerOutput_Period_BitfieldOffset) << kTimerOutput_Period_FixedPointIntegerShift;
482 return (int)((bitfieldValue) & 0x00FFFFFF);
483 }
484 public byte readTimerOutput_Count()
485 {
486
487 int result = NiFpga.readU32(m_DeviceHandle, kTimerOutput_Addresses[m_SystemIndex], status);
488 int regValue = result ;
489 int bitfieldValue = ((regValue & kTimerOutput_Count_BitfieldMask) >>> kTimerOutput_Count_BitfieldOffset);
490 // Sign extension
491 bitfieldValue <<= 24;
492 bitfieldValue >>= 24;
493 return (byte)(bitfieldValue);
494 }
495 public boolean readTimerOutput_Stalled()
496 {
497
498 int result = NiFpga.readU32(m_DeviceHandle, kTimerOutput_Addresses[m_SystemIndex], status);
499 int regValue = result ;
500 int bitfieldValue = ((regValue & kTimerOutput_Stalled_BitfieldMask) >>> kTimerOutput_Stalled_BitfieldOffset);
501 return ((bitfieldValue) != 0 ? true : false);
502 }
503
504 //////////////////////////////////////////////////////////////////////////////////////////////////
505 // Accessors for Reset
506 //////////////////////////////////////////////////////////////////////////////////////////////////
507 private static final int kCounter0_Reset_Address = 0x82E4;
508 private static final int kCounter1_Reset_Address = 0x82F8;
509 private static final int kCounter2_Reset_Address = 0x830C;
510 private static final int kCounter3_Reset_Address = 0x8320;
511 private static final int kCounter4_Reset_Address = 0x8334;
512 private static final int kCounter5_Reset_Address = 0x8348;
513 private static final int kCounter6_Reset_Address = 0x835C;
514 private static final int kCounter7_Reset_Address = 0x8370;
515 private static final int kReset_Addresses [] =
516 {
517 kCounter0_Reset_Address,
518 kCounter1_Reset_Address,
519 kCounter2_Reset_Address,
520 kCounter3_Reset_Address,
521 kCounter4_Reset_Address,
522 kCounter5_Reset_Address,
523 kCounter6_Reset_Address,
524 kCounter7_Reset_Address,
525 };
526
527 public void strobeReset()
528 {
529
530 NiFpga.writeU32(m_DeviceHandle, kReset_Addresses[m_SystemIndex], 1, status);
531 }
532
533 //////////////////////////////////////////////////////////////////////////////////////////////////
534 // Accessors for TimerConfig
535 //////////////////////////////////////////////////////////////////////////////////////////////////
536 private static final int kTimerConfig_StallPeriod_BitfieldMask = 0xFFFFFF00;
537 private static final int kTimerConfig_StallPeriod_BitfieldOffset = 8;
538 private static final int kTimerConfig_StallPeriod_FixedPointIntegerShift = 1;
539 private static final int kTimerConfig_AverageSize_BitfieldMask = 0x000000FE;
540 private static final int kTimerConfig_AverageSize_BitfieldOffset = 1;
541 private static final int kTimerConfig_UpdateWhenEmpty_BitfieldMask = 0x00000001;
542 private static final int kTimerConfig_UpdateWhenEmpty_BitfieldOffset = 0;
543 private static final int kCounter0_TimerConfig_Address = 0x82EC;
544 private static final int kCounter1_TimerConfig_Address = 0x8300;
545 private static final int kCounter2_TimerConfig_Address = 0x8314;
546 private static final int kCounter3_TimerConfig_Address = 0x8328;
547 private static final int kCounter4_TimerConfig_Address = 0x833C;
548 private static final int kCounter5_TimerConfig_Address = 0x8350;
549 private static final int kCounter6_TimerConfig_Address = 0x8364;
550 private static final int kCounter7_TimerConfig_Address = 0x8378;
551 private static final int kTimerConfig_Addresses [] =
552 {
553 kCounter0_TimerConfig_Address,
554 kCounter1_TimerConfig_Address,
555 kCounter2_TimerConfig_Address,
556 kCounter3_TimerConfig_Address,
557 kCounter4_TimerConfig_Address,
558 kCounter5_TimerConfig_Address,
559 kCounter6_TimerConfig_Address,
560 kCounter7_TimerConfig_Address,
561 };
562
563 public void writeTimerConfig(final int value)
564 {
565
566 NiFpga.writeU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], value, status);
567 }
568 public void writeTimerConfig_StallPeriod(final int value)
569 {
570
571 int regValue = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
572 regValue &= ~kTimerConfig_StallPeriod_BitfieldMask;
573 regValue |= ((value >>> kTimerConfig_StallPeriod_FixedPointIntegerShift) << kTimerConfig_StallPeriod_BitfieldOffset) & kTimerConfig_StallPeriod_BitfieldMask;
574 NiFpga.writeU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], regValue, status);
575 }
576 public void writeTimerConfig_AverageSize(final int value)
577 {
578
579 int regValue = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
580 regValue &= ~kTimerConfig_AverageSize_BitfieldMask;
581 regValue |= ((value) << kTimerConfig_AverageSize_BitfieldOffset) & kTimerConfig_AverageSize_BitfieldMask;
582 NiFpga.writeU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], regValue, status);
583 }
584 public void writeTimerConfig_UpdateWhenEmpty(final boolean value)
585 {
586
587 int regValue = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
588 regValue &= ~kTimerConfig_UpdateWhenEmpty_BitfieldMask;
589 regValue |= (((value ? 1 : 0)) << kTimerConfig_UpdateWhenEmpty_BitfieldOffset) & kTimerConfig_UpdateWhenEmpty_BitfieldMask;
590 NiFpga.writeU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], regValue, status);
591 }
592 public int readTimerConfig()
593 {
594
595 int result = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
596 int regValue = result ;
597 return (int)(regValue);
598 }
599 public int readTimerConfig_StallPeriod()
600 {
601
602 int result = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
603 int regValue = result ;
604 int bitfieldValue = ((regValue & kTimerConfig_StallPeriod_BitfieldMask) >>> kTimerConfig_StallPeriod_BitfieldOffset) << kTimerConfig_StallPeriod_FixedPointIntegerShift;
605 return (int)((bitfieldValue) & 0x01FFFFFF);
606 }
607 public byte readTimerConfig_AverageSize()
608 {
609
610 int result = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
611 int regValue = result ;
612 int bitfieldValue = ((regValue & kTimerConfig_AverageSize_BitfieldMask) >>> kTimerConfig_AverageSize_BitfieldOffset);
613 return (byte)((bitfieldValue) & 0x0000007F);
614 }
615 public boolean readTimerConfig_UpdateWhenEmpty()
616 {
617
618 int result = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
619 int regValue = result ;
620 int bitfieldValue = ((regValue & kTimerConfig_UpdateWhenEmpty_BitfieldMask) >>> kTimerConfig_UpdateWhenEmpty_BitfieldOffset);
621 return ((bitfieldValue) != 0 ? true : false);
622 }
623
624
625
626
627
628 }