001 // Copyright (c) National Instruments 2009. All Rights Reserved.
002 // Do Not Edit... this file is generated!
003
004 package edu.wpi.first.wpilibj.fpga;
005
006 import com.ni.rio.*;
007
008 public class tDMA extends tSystem
009 {
010
011 public tDMA()
012 {
013 super();
014
015 }
016
017 protected void finalize()
018 {
019 super.finalize();
020 }
021
022 public static final int kNumSystems = 1;
023
024
025
026
027
028
029
030 //////////////////////////////////////////////////////////////////////////////////////////////////
031 // Accessors for Rate
032 //////////////////////////////////////////////////////////////////////////////////////////////////
033 private static final int kDMA_Rate_Address = 0x8410;
034
035 public static void writeRate(final long value)
036 {
037
038 NiFpga.writeU32(m_DeviceHandle, kDMA_Rate_Address, (int)(value), status);
039 }
040 public static long readRate()
041 {
042
043 return (long)((NiFpga.readU32(m_DeviceHandle, kDMA_Rate_Address, status)) & 0xFFFFFFFFl);
044 }
045
046 //////////////////////////////////////////////////////////////////////////////////////////////////
047 // Accessors for Config
048 //////////////////////////////////////////////////////////////////////////////////////////////////
049 private static final int kConfig_Pause_BitfieldMask = 0x00080000;
050 private static final int kConfig_Pause_BitfieldOffset = 19;
051 private static final int kConfig_Enable_AI0_Low_BitfieldMask = 0x00040000;
052 private static final int kConfig_Enable_AI0_Low_BitfieldOffset = 18;
053 private static final int kConfig_Enable_AI0_High_BitfieldMask = 0x00020000;
054 private static final int kConfig_Enable_AI0_High_BitfieldOffset = 17;
055 private static final int kConfig_Enable_AIAveraged0_Low_BitfieldMask = 0x00010000;
056 private static final int kConfig_Enable_AIAveraged0_Low_BitfieldOffset = 16;
057 private static final int kConfig_Enable_AIAveraged0_High_BitfieldMask = 0x00008000;
058 private static final int kConfig_Enable_AIAveraged0_High_BitfieldOffset = 15;
059 private static final int kConfig_Enable_AI1_Low_BitfieldMask = 0x00004000;
060 private static final int kConfig_Enable_AI1_Low_BitfieldOffset = 14;
061 private static final int kConfig_Enable_AI1_High_BitfieldMask = 0x00002000;
062 private static final int kConfig_Enable_AI1_High_BitfieldOffset = 13;
063 private static final int kConfig_Enable_AIAveraged1_Low_BitfieldMask = 0x00001000;
064 private static final int kConfig_Enable_AIAveraged1_Low_BitfieldOffset = 12;
065 private static final int kConfig_Enable_AIAveraged1_High_BitfieldMask = 0x00000800;
066 private static final int kConfig_Enable_AIAveraged1_High_BitfieldOffset = 11;
067 private static final int kConfig_Enable_Accumulator0_BitfieldMask = 0x00000400;
068 private static final int kConfig_Enable_Accumulator0_BitfieldOffset = 10;
069 private static final int kConfig_Enable_Accumulator1_BitfieldMask = 0x00000200;
070 private static final int kConfig_Enable_Accumulator1_BitfieldOffset = 9;
071 private static final int kConfig_Enable_DI_BitfieldMask = 0x00000100;
072 private static final int kConfig_Enable_DI_BitfieldOffset = 8;
073 private static final int kConfig_Enable_AnalogTriggers_BitfieldMask = 0x00000080;
074 private static final int kConfig_Enable_AnalogTriggers_BitfieldOffset = 7;
075 private static final int kConfig_Enable_Counters_Low_BitfieldMask = 0x00000040;
076 private static final int kConfig_Enable_Counters_Low_BitfieldOffset = 6;
077 private static final int kConfig_Enable_Counters_High_BitfieldMask = 0x00000020;
078 private static final int kConfig_Enable_Counters_High_BitfieldOffset = 5;
079 private static final int kConfig_Enable_CounterTimers_Low_BitfieldMask = 0x00000010;
080 private static final int kConfig_Enable_CounterTimers_Low_BitfieldOffset = 4;
081 private static final int kConfig_Enable_CounterTimers_High_BitfieldMask = 0x00000008;
082 private static final int kConfig_Enable_CounterTimers_High_BitfieldOffset = 3;
083 private static final int kConfig_Enable_Encoders_BitfieldMask = 0x00000004;
084 private static final int kConfig_Enable_Encoders_BitfieldOffset = 2;
085 private static final int kConfig_Enable_EncoderTimers_BitfieldMask = 0x00000002;
086 private static final int kConfig_Enable_EncoderTimers_BitfieldOffset = 1;
087 private static final int kConfig_ExternalClock_BitfieldMask = 0x00000001;
088 private static final int kConfig_ExternalClock_BitfieldOffset = 0;
089 private static final int kDMA_Config_Address = 0x8414;
090
091 public static void writeConfig(final int value)
092 {
093
094 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, value, status);
095 }
096 public static void writeConfig_Pause(final boolean value)
097 {
098
099 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
100 regValue &= ~kConfig_Pause_BitfieldMask;
101 regValue |= (((value ? 1 : 0)) << kConfig_Pause_BitfieldOffset) & kConfig_Pause_BitfieldMask;
102 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
103 }
104 public static void writeConfig_Enable_AI0_Low(final boolean value)
105 {
106
107 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
108 regValue &= ~kConfig_Enable_AI0_Low_BitfieldMask;
109 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AI0_Low_BitfieldOffset) & kConfig_Enable_AI0_Low_BitfieldMask;
110 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
111 }
112 public static void writeConfig_Enable_AI0_High(final boolean value)
113 {
114
115 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
116 regValue &= ~kConfig_Enable_AI0_High_BitfieldMask;
117 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AI0_High_BitfieldOffset) & kConfig_Enable_AI0_High_BitfieldMask;
118 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
119 }
120 public static void writeConfig_Enable_AIAveraged0_Low(final boolean value)
121 {
122
123 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
124 regValue &= ~kConfig_Enable_AIAveraged0_Low_BitfieldMask;
125 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AIAveraged0_Low_BitfieldOffset) & kConfig_Enable_AIAveraged0_Low_BitfieldMask;
126 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
127 }
128 public static void writeConfig_Enable_AIAveraged0_High(final boolean value)
129 {
130
131 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
132 regValue &= ~kConfig_Enable_AIAveraged0_High_BitfieldMask;
133 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AIAveraged0_High_BitfieldOffset) & kConfig_Enable_AIAveraged0_High_BitfieldMask;
134 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
135 }
136 public static void writeConfig_Enable_AI1_Low(final boolean value)
137 {
138
139 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
140 regValue &= ~kConfig_Enable_AI1_Low_BitfieldMask;
141 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AI1_Low_BitfieldOffset) & kConfig_Enable_AI1_Low_BitfieldMask;
142 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
143 }
144 public static void writeConfig_Enable_AI1_High(final boolean value)
145 {
146
147 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
148 regValue &= ~kConfig_Enable_AI1_High_BitfieldMask;
149 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AI1_High_BitfieldOffset) & kConfig_Enable_AI1_High_BitfieldMask;
150 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
151 }
152 public static void writeConfig_Enable_AIAveraged1_Low(final boolean value)
153 {
154
155 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
156 regValue &= ~kConfig_Enable_AIAveraged1_Low_BitfieldMask;
157 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AIAveraged1_Low_BitfieldOffset) & kConfig_Enable_AIAveraged1_Low_BitfieldMask;
158 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
159 }
160 public static void writeConfig_Enable_AIAveraged1_High(final boolean value)
161 {
162
163 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
164 regValue &= ~kConfig_Enable_AIAveraged1_High_BitfieldMask;
165 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AIAveraged1_High_BitfieldOffset) & kConfig_Enable_AIAveraged1_High_BitfieldMask;
166 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
167 }
168 public static void writeConfig_Enable_Accumulator0(final boolean value)
169 {
170
171 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
172 regValue &= ~kConfig_Enable_Accumulator0_BitfieldMask;
173 regValue |= (((value ? 1 : 0)) << kConfig_Enable_Accumulator0_BitfieldOffset) & kConfig_Enable_Accumulator0_BitfieldMask;
174 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
175 }
176 public static void writeConfig_Enable_Accumulator1(final boolean value)
177 {
178
179 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
180 regValue &= ~kConfig_Enable_Accumulator1_BitfieldMask;
181 regValue |= (((value ? 1 : 0)) << kConfig_Enable_Accumulator1_BitfieldOffset) & kConfig_Enable_Accumulator1_BitfieldMask;
182 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
183 }
184 public static void writeConfig_Enable_DI(final boolean value)
185 {
186
187 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
188 regValue &= ~kConfig_Enable_DI_BitfieldMask;
189 regValue |= (((value ? 1 : 0)) << kConfig_Enable_DI_BitfieldOffset) & kConfig_Enable_DI_BitfieldMask;
190 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
191 }
192 public static void writeConfig_Enable_AnalogTriggers(final boolean value)
193 {
194
195 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
196 regValue &= ~kConfig_Enable_AnalogTriggers_BitfieldMask;
197 regValue |= (((value ? 1 : 0)) << kConfig_Enable_AnalogTriggers_BitfieldOffset) & kConfig_Enable_AnalogTriggers_BitfieldMask;
198 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
199 }
200 public static void writeConfig_Enable_Counters_Low(final boolean value)
201 {
202
203 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
204 regValue &= ~kConfig_Enable_Counters_Low_BitfieldMask;
205 regValue |= (((value ? 1 : 0)) << kConfig_Enable_Counters_Low_BitfieldOffset) & kConfig_Enable_Counters_Low_BitfieldMask;
206 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
207 }
208 public static void writeConfig_Enable_Counters_High(final boolean value)
209 {
210
211 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
212 regValue &= ~kConfig_Enable_Counters_High_BitfieldMask;
213 regValue |= (((value ? 1 : 0)) << kConfig_Enable_Counters_High_BitfieldOffset) & kConfig_Enable_Counters_High_BitfieldMask;
214 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
215 }
216 public static void writeConfig_Enable_CounterTimers_Low(final boolean value)
217 {
218
219 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
220 regValue &= ~kConfig_Enable_CounterTimers_Low_BitfieldMask;
221 regValue |= (((value ? 1 : 0)) << kConfig_Enable_CounterTimers_Low_BitfieldOffset) & kConfig_Enable_CounterTimers_Low_BitfieldMask;
222 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
223 }
224 public static void writeConfig_Enable_CounterTimers_High(final boolean value)
225 {
226
227 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
228 regValue &= ~kConfig_Enable_CounterTimers_High_BitfieldMask;
229 regValue |= (((value ? 1 : 0)) << kConfig_Enable_CounterTimers_High_BitfieldOffset) & kConfig_Enable_CounterTimers_High_BitfieldMask;
230 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
231 }
232 public static void writeConfig_Enable_Encoders(final boolean value)
233 {
234
235 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
236 regValue &= ~kConfig_Enable_Encoders_BitfieldMask;
237 regValue |= (((value ? 1 : 0)) << kConfig_Enable_Encoders_BitfieldOffset) & kConfig_Enable_Encoders_BitfieldMask;
238 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
239 }
240 public static void writeConfig_Enable_EncoderTimers(final boolean value)
241 {
242
243 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
244 regValue &= ~kConfig_Enable_EncoderTimers_BitfieldMask;
245 regValue |= (((value ? 1 : 0)) << kConfig_Enable_EncoderTimers_BitfieldOffset) & kConfig_Enable_EncoderTimers_BitfieldMask;
246 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
247 }
248 public static void writeConfig_ExternalClock(final boolean value)
249 {
250
251 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
252 regValue &= ~kConfig_ExternalClock_BitfieldMask;
253 regValue |= (((value ? 1 : 0)) << kConfig_ExternalClock_BitfieldOffset) & kConfig_ExternalClock_BitfieldMask;
254 NiFpga.writeU32(m_DeviceHandle, kDMA_Config_Address, regValue, status);
255 }
256 public static int readConfig()
257 {
258
259 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
260 int regValue = result ;
261 return (int)(regValue);
262 }
263 public static boolean readConfig_Pause()
264 {
265
266 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
267 int regValue = result ;
268 int bitfieldValue = ((regValue & kConfig_Pause_BitfieldMask) >>> kConfig_Pause_BitfieldOffset);
269 return ((bitfieldValue) != 0 ? true : false);
270 }
271 public static boolean readConfig_Enable_AI0_Low()
272 {
273
274 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
275 int regValue = result ;
276 int bitfieldValue = ((regValue & kConfig_Enable_AI0_Low_BitfieldMask) >>> kConfig_Enable_AI0_Low_BitfieldOffset);
277 return ((bitfieldValue) != 0 ? true : false);
278 }
279 public static boolean readConfig_Enable_AI0_High()
280 {
281
282 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
283 int regValue = result ;
284 int bitfieldValue = ((regValue & kConfig_Enable_AI0_High_BitfieldMask) >>> kConfig_Enable_AI0_High_BitfieldOffset);
285 return ((bitfieldValue) != 0 ? true : false);
286 }
287 public static boolean readConfig_Enable_AIAveraged0_Low()
288 {
289
290 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
291 int regValue = result ;
292 int bitfieldValue = ((regValue & kConfig_Enable_AIAveraged0_Low_BitfieldMask) >>> kConfig_Enable_AIAveraged0_Low_BitfieldOffset);
293 return ((bitfieldValue) != 0 ? true : false);
294 }
295 public static boolean readConfig_Enable_AIAveraged0_High()
296 {
297
298 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
299 int regValue = result ;
300 int bitfieldValue = ((regValue & kConfig_Enable_AIAveraged0_High_BitfieldMask) >>> kConfig_Enable_AIAveraged0_High_BitfieldOffset);
301 return ((bitfieldValue) != 0 ? true : false);
302 }
303 public static boolean readConfig_Enable_AI1_Low()
304 {
305
306 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
307 int regValue = result ;
308 int bitfieldValue = ((regValue & kConfig_Enable_AI1_Low_BitfieldMask) >>> kConfig_Enable_AI1_Low_BitfieldOffset);
309 return ((bitfieldValue) != 0 ? true : false);
310 }
311 public static boolean readConfig_Enable_AI1_High()
312 {
313
314 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
315 int regValue = result ;
316 int bitfieldValue = ((regValue & kConfig_Enable_AI1_High_BitfieldMask) >>> kConfig_Enable_AI1_High_BitfieldOffset);
317 return ((bitfieldValue) != 0 ? true : false);
318 }
319 public static boolean readConfig_Enable_AIAveraged1_Low()
320 {
321
322 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
323 int regValue = result ;
324 int bitfieldValue = ((regValue & kConfig_Enable_AIAveraged1_Low_BitfieldMask) >>> kConfig_Enable_AIAveraged1_Low_BitfieldOffset);
325 return ((bitfieldValue) != 0 ? true : false);
326 }
327 public static boolean readConfig_Enable_AIAveraged1_High()
328 {
329
330 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
331 int regValue = result ;
332 int bitfieldValue = ((regValue & kConfig_Enable_AIAveraged1_High_BitfieldMask) >>> kConfig_Enable_AIAveraged1_High_BitfieldOffset);
333 return ((bitfieldValue) != 0 ? true : false);
334 }
335 public static boolean readConfig_Enable_Accumulator0()
336 {
337
338 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
339 int regValue = result ;
340 int bitfieldValue = ((regValue & kConfig_Enable_Accumulator0_BitfieldMask) >>> kConfig_Enable_Accumulator0_BitfieldOffset);
341 return ((bitfieldValue) != 0 ? true : false);
342 }
343 public static boolean readConfig_Enable_Accumulator1()
344 {
345
346 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
347 int regValue = result ;
348 int bitfieldValue = ((regValue & kConfig_Enable_Accumulator1_BitfieldMask) >>> kConfig_Enable_Accumulator1_BitfieldOffset);
349 return ((bitfieldValue) != 0 ? true : false);
350 }
351 public static boolean readConfig_Enable_DI()
352 {
353
354 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
355 int regValue = result ;
356 int bitfieldValue = ((regValue & kConfig_Enable_DI_BitfieldMask) >>> kConfig_Enable_DI_BitfieldOffset);
357 return ((bitfieldValue) != 0 ? true : false);
358 }
359 public static boolean readConfig_Enable_AnalogTriggers()
360 {
361
362 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
363 int regValue = result ;
364 int bitfieldValue = ((regValue & kConfig_Enable_AnalogTriggers_BitfieldMask) >>> kConfig_Enable_AnalogTriggers_BitfieldOffset);
365 return ((bitfieldValue) != 0 ? true : false);
366 }
367 public static boolean readConfig_Enable_Counters_Low()
368 {
369
370 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
371 int regValue = result ;
372 int bitfieldValue = ((regValue & kConfig_Enable_Counters_Low_BitfieldMask) >>> kConfig_Enable_Counters_Low_BitfieldOffset);
373 return ((bitfieldValue) != 0 ? true : false);
374 }
375 public static boolean readConfig_Enable_Counters_High()
376 {
377
378 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
379 int regValue = result ;
380 int bitfieldValue = ((regValue & kConfig_Enable_Counters_High_BitfieldMask) >>> kConfig_Enable_Counters_High_BitfieldOffset);
381 return ((bitfieldValue) != 0 ? true : false);
382 }
383 public static boolean readConfig_Enable_CounterTimers_Low()
384 {
385
386 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
387 int regValue = result ;
388 int bitfieldValue = ((regValue & kConfig_Enable_CounterTimers_Low_BitfieldMask) >>> kConfig_Enable_CounterTimers_Low_BitfieldOffset);
389 return ((bitfieldValue) != 0 ? true : false);
390 }
391 public static boolean readConfig_Enable_CounterTimers_High()
392 {
393
394 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
395 int regValue = result ;
396 int bitfieldValue = ((regValue & kConfig_Enable_CounterTimers_High_BitfieldMask) >>> kConfig_Enable_CounterTimers_High_BitfieldOffset);
397 return ((bitfieldValue) != 0 ? true : false);
398 }
399 public static boolean readConfig_Enable_Encoders()
400 {
401
402 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
403 int regValue = result ;
404 int bitfieldValue = ((regValue & kConfig_Enable_Encoders_BitfieldMask) >>> kConfig_Enable_Encoders_BitfieldOffset);
405 return ((bitfieldValue) != 0 ? true : false);
406 }
407 public static boolean readConfig_Enable_EncoderTimers()
408 {
409
410 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
411 int regValue = result ;
412 int bitfieldValue = ((regValue & kConfig_Enable_EncoderTimers_BitfieldMask) >>> kConfig_Enable_EncoderTimers_BitfieldOffset);
413 return ((bitfieldValue) != 0 ? true : false);
414 }
415 public static boolean readConfig_ExternalClock()
416 {
417
418 int result = NiFpga.readU32(m_DeviceHandle, kDMA_Config_Address, status);
419 int regValue = result ;
420 int bitfieldValue = ((regValue & kConfig_ExternalClock_BitfieldMask) >>> kConfig_ExternalClock_BitfieldOffset);
421 return ((bitfieldValue) != 0 ? true : false);
422 }
423
424 //////////////////////////////////////////////////////////////////////////////////////////////////
425 // Accessors for ExternalTriggers
426 //////////////////////////////////////////////////////////////////////////////////////////////////
427 public static final int kExternalTriggers_NumElements = 4;
428 public static final int kExternalTriggers_ElementSize = 8;
429 public static final int kExternalTriggers_ElementMask = 0xFF;
430 private static final int kExternalTriggers_ExternalClockSource_Channel_BitfieldMask = 0x000000F0;
431 private static final int kExternalTriggers_ExternalClockSource_Channel_BitfieldOffset = 4;
432 private static final int kExternalTriggers_ExternalClockSource_Module_BitfieldMask = 0x00000008;
433 private static final int kExternalTriggers_ExternalClockSource_Module_BitfieldOffset = 3;
434 private static final int kExternalTriggers_ExternalClockSource_AnalogTrigger_BitfieldMask = 0x00000004;
435 private static final int kExternalTriggers_ExternalClockSource_AnalogTrigger_BitfieldOffset = 2;
436 private static final int kExternalTriggers_RisingEdge_BitfieldMask = 0x00000002;
437 private static final int kExternalTriggers_RisingEdge_BitfieldOffset = 1;
438 private static final int kExternalTriggers_FallingEdge_BitfieldMask = 0x00000001;
439 private static final int kExternalTriggers_FallingEdge_BitfieldOffset = 0;
440 private static final int kDMA_ExternalTriggers_Address = 0x844C;
441
442 public static void writeExternalTriggers(final int bitfield_index, final int value)
443 {
444 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
445 {
446 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
447 }
448
449 NiFpga.writeU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, value, status);
450 }
451 public static void writeExternalTriggers_ExternalClockSource_Channel(final int bitfield_index, final int value)
452 {
453 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
454 {
455 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
456 }
457
458 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
459 regValue &= ~kExternalTriggers_ExternalClockSource_Channel_BitfieldMask;
460 regValue |= ((value) << kExternalTriggers_ExternalClockSource_Channel_BitfieldOffset) & kExternalTriggers_ExternalClockSource_Channel_BitfieldMask;
461 NiFpga.writeU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, regValue, status);
462 }
463 public static void writeExternalTriggers_ExternalClockSource_Module(final int bitfield_index, final int value)
464 {
465 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
466 {
467 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
468 }
469
470 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
471 regValue &= ~kExternalTriggers_ExternalClockSource_Module_BitfieldMask;
472 regValue |= ((value) << kExternalTriggers_ExternalClockSource_Module_BitfieldOffset) & kExternalTriggers_ExternalClockSource_Module_BitfieldMask;
473 NiFpga.writeU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, regValue, status);
474 }
475 public static void writeExternalTriggers_ExternalClockSource_AnalogTrigger(final int bitfield_index, final boolean value)
476 {
477 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
478 {
479 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
480 }
481
482 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
483 regValue &= ~kExternalTriggers_ExternalClockSource_AnalogTrigger_BitfieldMask;
484 regValue |= (((value ? 1 : 0)) << kExternalTriggers_ExternalClockSource_AnalogTrigger_BitfieldOffset) & kExternalTriggers_ExternalClockSource_AnalogTrigger_BitfieldMask;
485 NiFpga.writeU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, regValue, status);
486 }
487 public static void writeExternalTriggers_RisingEdge(final int bitfield_index, final boolean value)
488 {
489 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
490 {
491 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
492 }
493
494 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
495 regValue &= ~kExternalTriggers_RisingEdge_BitfieldMask;
496 regValue |= (((value ? 1 : 0)) << kExternalTriggers_RisingEdge_BitfieldOffset) & kExternalTriggers_RisingEdge_BitfieldMask;
497 NiFpga.writeU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, regValue, status);
498 }
499 public static void writeExternalTriggers_FallingEdge(final int bitfield_index, final boolean value)
500 {
501 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
502 {
503 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
504 }
505
506 int regValue = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
507 regValue &= ~kExternalTriggers_FallingEdge_BitfieldMask;
508 regValue |= (((value ? 1 : 0)) << kExternalTriggers_FallingEdge_BitfieldOffset) & kExternalTriggers_FallingEdge_BitfieldMask;
509 NiFpga.writeU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, regValue, status);
510 }
511 public static int readExternalTriggers(final int bitfield_index)
512 {
513 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
514 {
515 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
516 }
517
518 int result = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
519 int regValue = result >>> ((kExternalTriggers_NumElements - 1 - bitfield_index) * kExternalTriggers_ElementSize);
520 return (int)(regValue);
521 }
522 public static byte readExternalTriggers_ExternalClockSource_Channel(final int bitfield_index)
523 {
524 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
525 {
526 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
527 }
528
529 int result = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
530 int regValue = result >>> ((kExternalTriggers_NumElements - 1 - bitfield_index) * kExternalTriggers_ElementSize);
531 int bitfieldValue = ((regValue & kExternalTriggers_ExternalClockSource_Channel_BitfieldMask) >>> kExternalTriggers_ExternalClockSource_Channel_BitfieldOffset);
532 return (byte)((bitfieldValue) & 0x0000000F);
533 }
534 public static byte readExternalTriggers_ExternalClockSource_Module(final int bitfield_index)
535 {
536 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
537 {
538 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
539 }
540
541 int result = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
542 int regValue = result >>> ((kExternalTriggers_NumElements - 1 - bitfield_index) * kExternalTriggers_ElementSize);
543 int bitfieldValue = ((regValue & kExternalTriggers_ExternalClockSource_Module_BitfieldMask) >>> kExternalTriggers_ExternalClockSource_Module_BitfieldOffset);
544 return (byte)((bitfieldValue) & 0x00000001);
545 }
546 public static boolean readExternalTriggers_ExternalClockSource_AnalogTrigger(final int bitfield_index)
547 {
548 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
549 {
550 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
551 }
552
553 int result = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
554 int regValue = result >>> ((kExternalTriggers_NumElements - 1 - bitfield_index) * kExternalTriggers_ElementSize);
555 int bitfieldValue = ((regValue & kExternalTriggers_ExternalClockSource_AnalogTrigger_BitfieldMask) >>> kExternalTriggers_ExternalClockSource_AnalogTrigger_BitfieldOffset);
556 return ((bitfieldValue) != 0 ? true : false);
557 }
558 public static boolean readExternalTriggers_RisingEdge(final int bitfield_index)
559 {
560 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
561 {
562 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
563 }
564
565 int result = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
566 int regValue = result >>> ((kExternalTriggers_NumElements - 1 - bitfield_index) * kExternalTriggers_ElementSize);
567 int bitfieldValue = ((regValue & kExternalTriggers_RisingEdge_BitfieldMask) >>> kExternalTriggers_RisingEdge_BitfieldOffset);
568 return ((bitfieldValue) != 0 ? true : false);
569 }
570 public static boolean readExternalTriggers_FallingEdge(final int bitfield_index)
571 {
572 if (status.isNotFatal() && bitfield_index >= kExternalTriggers_NumElements)
573 {
574 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
575 }
576
577 int result = NiFpga.readU32(m_DeviceHandle, kDMA_ExternalTriggers_Address, status);
578 int regValue = result >>> ((kExternalTriggers_NumElements - 1 - bitfield_index) * kExternalTriggers_ElementSize);
579 int bitfieldValue = ((regValue & kExternalTriggers_FallingEdge_BitfieldMask) >>> kExternalTriggers_FallingEdge_BitfieldOffset);
580 return ((bitfieldValue) != 0 ? true : false);
581 }
582
583
584
585
586 }