001    // Class for handling DMA transters.
002    // Copyright (c) National Instruments 2008.  All Rights Reserved.
003    
004    package edu.wpi.first.wpilibj.fpga;
005    
006    import com.ni.rio.*;
007    import com.sun.cldc.jna.*;
008    import com.sun.cldc.jna.ptr.IntByReference;
009    
010    public class tDMAManager extends tSystem
011    {
012    
013       boolean m_started;
014       int m_dmaChannel;
015       int m_hostBufferSize;
016       //DMAChannelDescriptors.tDMAChannelDescriptor m_dmaChannelDescriptor;
017    
018       public tDMAManager(int dmaChannel, int hostBufferSize)
019       {
020          super();
021          if (status.isFatal()) return;
022    
023          /*
024          m_started = false;
025          m_dmaChannel = dmaChannel;
026          m_hostBufferSize = hostBufferSize;
027    
028          boolean found = false;
029          for (int i=0; i<kNUM_DMA_CHANNELS; i++)
030          {
031             if(kDMAChannelDescriptors[i].channel == m_dmaChannel)
032             {
033                m_dmaChannelDescriptor = kDMAChannelDescriptors[i];
034                found = true;
035                break;
036             }
037          }
038    
039          if(!found)
040          {
041             // The DMA channel is not defined in the bitfile.
042              status.setStatus(NiRioStatus.kRIOStatusBadSelector);
043              return;
044          }
045    
046          // Allocate the appropriate resources in the RIO driver.
047          NiFpga.configureFifo(m_DeviceHandle, m_dmaChannel, m_hostBufferSize, status);
048          */
049       }
050    
051       protected void finalize()
052       {
053              /*
054          stop();
055          super.finalize();
056          */
057       }
058    
059       public void start()
060       {
061              /*
062          NiFpga.startFifo(m_DeviceHandle, m_dmaChannel, status);
063          m_started = true;
064          */
065       }
066    
067       public void stop()
068       {
069              /*
070          NiFpga.stopFifo(m_DeviceHandle, m_dmaChannel, status);
071          m_started = false;
072          */
073       }
074    
075       public int[] read(
076          int       num,
077          int       timeout)
078       {
079              /*  
080          // Ensure that the FPGA is writing so that the host can read
081          if(m_dmaChannelDescriptor.write != 1)
082          {
083             status.setStatus(NiRioStatus.kRIOStatusInvalidFunction);
084             return new int[0];
085          }
086    
087                    Pointer pBuffer = new Pointer(num * 4);
088          IntByReference remaining = new IntByReference(0);
089    
090          NiFpga.readFifoU32(m_DeviceHandle, m_dmaChannel, pBuffer, num, timeout, remaining, status);
091    
092          int[] data = new int[num];
093                    pBuffer.getInts(0, data, 0, num);
094                    pBuffer.free();
095    
096          m_started = true;
097    
098          return data;
099          */
100          return new int[0];
101       }
102    }