001 // Copyright (c) National Instruments 2009. All Rights Reserved.
002 // Do Not Edit... this file is generated!
003
004 package edu.wpi.first.wpilibj.fpga;
005
006 import com.ni.rio.*;
007
008 public class tEncoder extends tSystem
009 {
010
011 public tEncoder(final int sys_index)
012 {
013 super();
014 m_SystemIndex = sys_index;
015 if (status.isNotFatal() && m_SystemIndex >= kNumSystems)
016 {
017 status.setStatus(NiRioStatus.kRIOStatusBadSelector);
018 }
019
020 }
021
022 protected void finalize()
023 {
024 super.finalize();
025 }
026
027 public int getSystemIndex()
028 {
029 return m_SystemIndex;
030 }
031
032 public static final int kNumSystems = 4;
033 public final int m_SystemIndex;
034
035
036
037
038
039
040
041
042 //////////////////////////////////////////////////////////////////////////////////////////////////
043 // Accessors for Output
044 //////////////////////////////////////////////////////////////////////////////////////////////////
045 private static final int kOutput_Direction_BitfieldMask = 0x80000000;
046 private static final int kOutput_Direction_BitfieldOffset = 31;
047 private static final int kOutput_Value_BitfieldMask = 0x7FFFFFFF;
048 private static final int kOutput_Value_BitfieldOffset = 0;
049 private static final int kEncoder0_Output_Address = 0x8388;
050 private static final int kEncoder1_Output_Address = 0x839C;
051 private static final int kEncoder2_Output_Address = 0x83B0;
052 private static final int kEncoder3_Output_Address = 0x83C4;
053 private static final int kOutput_Addresses [] =
054 {
055 kEncoder0_Output_Address,
056 kEncoder1_Output_Address,
057 kEncoder2_Output_Address,
058 kEncoder3_Output_Address,
059 };
060
061 public int readOutput()
062 {
063
064 int result = NiFpga.readU32(m_DeviceHandle, kOutput_Addresses[m_SystemIndex], status);
065 int regValue = result ;
066 return (int)(regValue);
067 }
068 public boolean readOutput_Direction()
069 {
070
071 int result = NiFpga.readU32(m_DeviceHandle, kOutput_Addresses[m_SystemIndex], status);
072 int regValue = result ;
073 int bitfieldValue = ((regValue & kOutput_Direction_BitfieldMask) >>> kOutput_Direction_BitfieldOffset);
074 return ((bitfieldValue) != 0 ? true : false);
075 }
076 public int readOutput_Value()
077 {
078
079 int result = NiFpga.readU32(m_DeviceHandle, kOutput_Addresses[m_SystemIndex], status);
080 int regValue = result ;
081 int bitfieldValue = ((regValue & kOutput_Value_BitfieldMask) >>> kOutput_Value_BitfieldOffset);
082 // Sign extension
083 bitfieldValue <<= 1;
084 bitfieldValue >>= 1;
085 return (int)(bitfieldValue);
086 }
087
088 //////////////////////////////////////////////////////////////////////////////////////////////////
089 // Accessors for Config
090 //////////////////////////////////////////////////////////////////////////////////////////////////
091 private static final int kConfig_ASource_Channel_BitfieldMask = 0x001E0000;
092 private static final int kConfig_ASource_Channel_BitfieldOffset = 17;
093 private static final int kConfig_ASource_Module_BitfieldMask = 0x00010000;
094 private static final int kConfig_ASource_Module_BitfieldOffset = 16;
095 private static final int kConfig_ASource_AnalogTrigger_BitfieldMask = 0x00008000;
096 private static final int kConfig_ASource_AnalogTrigger_BitfieldOffset = 15;
097 private static final int kConfig_BSource_Channel_BitfieldMask = 0x00007800;
098 private static final int kConfig_BSource_Channel_BitfieldOffset = 11;
099 private static final int kConfig_BSource_Module_BitfieldMask = 0x00000400;
100 private static final int kConfig_BSource_Module_BitfieldOffset = 10;
101 private static final int kConfig_BSource_AnalogTrigger_BitfieldMask = 0x00000200;
102 private static final int kConfig_BSource_AnalogTrigger_BitfieldOffset = 9;
103 private static final int kConfig_IndexSource_Channel_BitfieldMask = 0x000001E0;
104 private static final int kConfig_IndexSource_Channel_BitfieldOffset = 5;
105 private static final int kConfig_IndexSource_Module_BitfieldMask = 0x00000010;
106 private static final int kConfig_IndexSource_Module_BitfieldOffset = 4;
107 private static final int kConfig_IndexSource_AnalogTrigger_BitfieldMask = 0x00000008;
108 private static final int kConfig_IndexSource_AnalogTrigger_BitfieldOffset = 3;
109 private static final int kConfig_IndexActiveHigh_BitfieldMask = 0x00000004;
110 private static final int kConfig_IndexActiveHigh_BitfieldOffset = 2;
111 private static final int kConfig_Reverse_BitfieldMask = 0x00000002;
112 private static final int kConfig_Reverse_BitfieldOffset = 1;
113 private static final int kConfig_Enable_BitfieldMask = 0x00000001;
114 private static final int kConfig_Enable_BitfieldOffset = 0;
115 private static final int kEncoder0_Config_Address = 0x8380;
116 private static final int kEncoder1_Config_Address = 0x8394;
117 private static final int kEncoder2_Config_Address = 0x83A8;
118 private static final int kEncoder3_Config_Address = 0x83BC;
119 private static final int kConfig_Addresses [] =
120 {
121 kEncoder0_Config_Address,
122 kEncoder1_Config_Address,
123 kEncoder2_Config_Address,
124 kEncoder3_Config_Address,
125 };
126
127 public void writeConfig(final int value)
128 {
129
130 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], value, status);
131 }
132 public void writeConfig_ASource_Channel(final int value)
133 {
134
135 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
136 regValue &= ~kConfig_ASource_Channel_BitfieldMask;
137 regValue |= ((value) << kConfig_ASource_Channel_BitfieldOffset) & kConfig_ASource_Channel_BitfieldMask;
138 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
139 }
140 public void writeConfig_ASource_Module(final int value)
141 {
142
143 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
144 regValue &= ~kConfig_ASource_Module_BitfieldMask;
145 regValue |= ((value) << kConfig_ASource_Module_BitfieldOffset) & kConfig_ASource_Module_BitfieldMask;
146 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
147 }
148 public void writeConfig_ASource_AnalogTrigger(final boolean value)
149 {
150
151 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
152 regValue &= ~kConfig_ASource_AnalogTrigger_BitfieldMask;
153 regValue |= (((value ? 1 : 0)) << kConfig_ASource_AnalogTrigger_BitfieldOffset) & kConfig_ASource_AnalogTrigger_BitfieldMask;
154 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
155 }
156 public void writeConfig_BSource_Channel(final int value)
157 {
158
159 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
160 regValue &= ~kConfig_BSource_Channel_BitfieldMask;
161 regValue |= ((value) << kConfig_BSource_Channel_BitfieldOffset) & kConfig_BSource_Channel_BitfieldMask;
162 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
163 }
164 public void writeConfig_BSource_Module(final int value)
165 {
166
167 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
168 regValue &= ~kConfig_BSource_Module_BitfieldMask;
169 regValue |= ((value) << kConfig_BSource_Module_BitfieldOffset) & kConfig_BSource_Module_BitfieldMask;
170 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
171 }
172 public void writeConfig_BSource_AnalogTrigger(final boolean value)
173 {
174
175 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
176 regValue &= ~kConfig_BSource_AnalogTrigger_BitfieldMask;
177 regValue |= (((value ? 1 : 0)) << kConfig_BSource_AnalogTrigger_BitfieldOffset) & kConfig_BSource_AnalogTrigger_BitfieldMask;
178 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
179 }
180 public void writeConfig_IndexSource_Channel(final int value)
181 {
182
183 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
184 regValue &= ~kConfig_IndexSource_Channel_BitfieldMask;
185 regValue |= ((value) << kConfig_IndexSource_Channel_BitfieldOffset) & kConfig_IndexSource_Channel_BitfieldMask;
186 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
187 }
188 public void writeConfig_IndexSource_Module(final int value)
189 {
190
191 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
192 regValue &= ~kConfig_IndexSource_Module_BitfieldMask;
193 regValue |= ((value) << kConfig_IndexSource_Module_BitfieldOffset) & kConfig_IndexSource_Module_BitfieldMask;
194 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
195 }
196 public void writeConfig_IndexSource_AnalogTrigger(final boolean value)
197 {
198
199 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
200 regValue &= ~kConfig_IndexSource_AnalogTrigger_BitfieldMask;
201 regValue |= (((value ? 1 : 0)) << kConfig_IndexSource_AnalogTrigger_BitfieldOffset) & kConfig_IndexSource_AnalogTrigger_BitfieldMask;
202 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
203 }
204 public void writeConfig_IndexActiveHigh(final boolean value)
205 {
206
207 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
208 regValue &= ~kConfig_IndexActiveHigh_BitfieldMask;
209 regValue |= (((value ? 1 : 0)) << kConfig_IndexActiveHigh_BitfieldOffset) & kConfig_IndexActiveHigh_BitfieldMask;
210 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
211 }
212 public void writeConfig_Reverse(final boolean value)
213 {
214
215 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
216 regValue &= ~kConfig_Reverse_BitfieldMask;
217 regValue |= (((value ? 1 : 0)) << kConfig_Reverse_BitfieldOffset) & kConfig_Reverse_BitfieldMask;
218 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
219 }
220 public void writeConfig_Enable(final boolean value)
221 {
222
223 int regValue = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
224 regValue &= ~kConfig_Enable_BitfieldMask;
225 regValue |= (((value ? 1 : 0)) << kConfig_Enable_BitfieldOffset) & kConfig_Enable_BitfieldMask;
226 NiFpga.writeU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], regValue, status);
227 }
228 public int readConfig()
229 {
230
231 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
232 int regValue = result ;
233 return (int)(regValue);
234 }
235 public byte readConfig_ASource_Channel()
236 {
237
238 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
239 int regValue = result ;
240 int bitfieldValue = ((regValue & kConfig_ASource_Channel_BitfieldMask) >>> kConfig_ASource_Channel_BitfieldOffset);
241 return (byte)((bitfieldValue) & 0x0000000F);
242 }
243 public byte readConfig_ASource_Module()
244 {
245
246 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
247 int regValue = result ;
248 int bitfieldValue = ((regValue & kConfig_ASource_Module_BitfieldMask) >>> kConfig_ASource_Module_BitfieldOffset);
249 return (byte)((bitfieldValue) & 0x00000001);
250 }
251 public boolean readConfig_ASource_AnalogTrigger()
252 {
253
254 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
255 int regValue = result ;
256 int bitfieldValue = ((regValue & kConfig_ASource_AnalogTrigger_BitfieldMask) >>> kConfig_ASource_AnalogTrigger_BitfieldOffset);
257 return ((bitfieldValue) != 0 ? true : false);
258 }
259 public byte readConfig_BSource_Channel()
260 {
261
262 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
263 int regValue = result ;
264 int bitfieldValue = ((regValue & kConfig_BSource_Channel_BitfieldMask) >>> kConfig_BSource_Channel_BitfieldOffset);
265 return (byte)((bitfieldValue) & 0x0000000F);
266 }
267 public byte readConfig_BSource_Module()
268 {
269
270 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
271 int regValue = result ;
272 int bitfieldValue = ((regValue & kConfig_BSource_Module_BitfieldMask) >>> kConfig_BSource_Module_BitfieldOffset);
273 return (byte)((bitfieldValue) & 0x00000001);
274 }
275 public boolean readConfig_BSource_AnalogTrigger()
276 {
277
278 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
279 int regValue = result ;
280 int bitfieldValue = ((regValue & kConfig_BSource_AnalogTrigger_BitfieldMask) >>> kConfig_BSource_AnalogTrigger_BitfieldOffset);
281 return ((bitfieldValue) != 0 ? true : false);
282 }
283 public byte readConfig_IndexSource_Channel()
284 {
285
286 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
287 int regValue = result ;
288 int bitfieldValue = ((regValue & kConfig_IndexSource_Channel_BitfieldMask) >>> kConfig_IndexSource_Channel_BitfieldOffset);
289 return (byte)((bitfieldValue) & 0x0000000F);
290 }
291 public byte readConfig_IndexSource_Module()
292 {
293
294 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
295 int regValue = result ;
296 int bitfieldValue = ((regValue & kConfig_IndexSource_Module_BitfieldMask) >>> kConfig_IndexSource_Module_BitfieldOffset);
297 return (byte)((bitfieldValue) & 0x00000001);
298 }
299 public boolean readConfig_IndexSource_AnalogTrigger()
300 {
301
302 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
303 int regValue = result ;
304 int bitfieldValue = ((regValue & kConfig_IndexSource_AnalogTrigger_BitfieldMask) >>> kConfig_IndexSource_AnalogTrigger_BitfieldOffset);
305 return ((bitfieldValue) != 0 ? true : false);
306 }
307 public boolean readConfig_IndexActiveHigh()
308 {
309
310 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
311 int regValue = result ;
312 int bitfieldValue = ((regValue & kConfig_IndexActiveHigh_BitfieldMask) >>> kConfig_IndexActiveHigh_BitfieldOffset);
313 return ((bitfieldValue) != 0 ? true : false);
314 }
315 public boolean readConfig_Reverse()
316 {
317
318 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
319 int regValue = result ;
320 int bitfieldValue = ((regValue & kConfig_Reverse_BitfieldMask) >>> kConfig_Reverse_BitfieldOffset);
321 return ((bitfieldValue) != 0 ? true : false);
322 }
323 public boolean readConfig_Enable()
324 {
325
326 int result = NiFpga.readU32(m_DeviceHandle, kConfig_Addresses[m_SystemIndex], status);
327 int regValue = result ;
328 int bitfieldValue = ((regValue & kConfig_Enable_BitfieldMask) >>> kConfig_Enable_BitfieldOffset);
329 return ((bitfieldValue) != 0 ? true : false);
330 }
331
332 //////////////////////////////////////////////////////////////////////////////////////////////////
333 // Accessors for TimerOutput
334 //////////////////////////////////////////////////////////////////////////////////////////////////
335 private static final int kTimerOutput_Period_BitfieldMask = 0xFFFFFE00;
336 private static final int kTimerOutput_Period_BitfieldOffset = 9;
337 private static final int kTimerOutput_Period_FixedPointIntegerShift = 1;
338 private static final int kTimerOutput_Count_BitfieldMask = 0x000001FE;
339 private static final int kTimerOutput_Count_BitfieldOffset = 1;
340 private static final int kTimerOutput_Stalled_BitfieldMask = 0x00000001;
341 private static final int kTimerOutput_Stalled_BitfieldOffset = 0;
342 private static final int kEncoder0_TimerOutput_Address = 0x8390;
343 private static final int kEncoder1_TimerOutput_Address = 0x83A4;
344 private static final int kEncoder2_TimerOutput_Address = 0x83B8;
345 private static final int kEncoder3_TimerOutput_Address = 0x83CC;
346 private static final int kTimerOutput_Addresses [] =
347 {
348 kEncoder0_TimerOutput_Address,
349 kEncoder1_TimerOutput_Address,
350 kEncoder2_TimerOutput_Address,
351 kEncoder3_TimerOutput_Address,
352 };
353
354 public int readTimerOutput()
355 {
356
357 int result = NiFpga.readU32(m_DeviceHandle, kTimerOutput_Addresses[m_SystemIndex], status);
358 int regValue = result ;
359 return (int)(regValue);
360 }
361 public int readTimerOutput_Period()
362 {
363
364 int result = NiFpga.readU32(m_DeviceHandle, kTimerOutput_Addresses[m_SystemIndex], status);
365 int regValue = result ;
366 int bitfieldValue = ((regValue & kTimerOutput_Period_BitfieldMask) >>> kTimerOutput_Period_BitfieldOffset) << kTimerOutput_Period_FixedPointIntegerShift;
367 return (int)((bitfieldValue) & 0x00FFFFFF);
368 }
369 public byte readTimerOutput_Count()
370 {
371
372 int result = NiFpga.readU32(m_DeviceHandle, kTimerOutput_Addresses[m_SystemIndex], status);
373 int regValue = result ;
374 int bitfieldValue = ((regValue & kTimerOutput_Count_BitfieldMask) >>> kTimerOutput_Count_BitfieldOffset);
375 // Sign extension
376 bitfieldValue <<= 24;
377 bitfieldValue >>= 24;
378 return (byte)(bitfieldValue);
379 }
380 public boolean readTimerOutput_Stalled()
381 {
382
383 int result = NiFpga.readU32(m_DeviceHandle, kTimerOutput_Addresses[m_SystemIndex], status);
384 int regValue = result ;
385 int bitfieldValue = ((regValue & kTimerOutput_Stalled_BitfieldMask) >>> kTimerOutput_Stalled_BitfieldOffset);
386 return ((bitfieldValue) != 0 ? true : false);
387 }
388
389 //////////////////////////////////////////////////////////////////////////////////////////////////
390 // Accessors for Reset
391 //////////////////////////////////////////////////////////////////////////////////////////////////
392 private static final int kEncoder0_Reset_Address = 0x8384;
393 private static final int kEncoder1_Reset_Address = 0x8398;
394 private static final int kEncoder2_Reset_Address = 0x83AC;
395 private static final int kEncoder3_Reset_Address = 0x83C0;
396 private static final int kReset_Addresses [] =
397 {
398 kEncoder0_Reset_Address,
399 kEncoder1_Reset_Address,
400 kEncoder2_Reset_Address,
401 kEncoder3_Reset_Address,
402 };
403
404 public void strobeReset()
405 {
406
407 NiFpga.writeU32(m_DeviceHandle, kReset_Addresses[m_SystemIndex], 1, status);
408 }
409
410 //////////////////////////////////////////////////////////////////////////////////////////////////
411 // Accessors for TimerConfig
412 //////////////////////////////////////////////////////////////////////////////////////////////////
413 private static final int kTimerConfig_StallPeriod_BitfieldMask = 0xFFFFFF00;
414 private static final int kTimerConfig_StallPeriod_BitfieldOffset = 8;
415 private static final int kTimerConfig_StallPeriod_FixedPointIntegerShift = 1;
416 private static final int kTimerConfig_AverageSize_BitfieldMask = 0x000000FE;
417 private static final int kTimerConfig_AverageSize_BitfieldOffset = 1;
418 private static final int kTimerConfig_UpdateWhenEmpty_BitfieldMask = 0x00000001;
419 private static final int kTimerConfig_UpdateWhenEmpty_BitfieldOffset = 0;
420 private static final int kEncoder0_TimerConfig_Address = 0x838C;
421 private static final int kEncoder1_TimerConfig_Address = 0x83A0;
422 private static final int kEncoder2_TimerConfig_Address = 0x83B4;
423 private static final int kEncoder3_TimerConfig_Address = 0x83C8;
424 private static final int kTimerConfig_Addresses [] =
425 {
426 kEncoder0_TimerConfig_Address,
427 kEncoder1_TimerConfig_Address,
428 kEncoder2_TimerConfig_Address,
429 kEncoder3_TimerConfig_Address,
430 };
431
432 public void writeTimerConfig(final int value)
433 {
434
435 NiFpga.writeU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], value, status);
436 }
437 public void writeTimerConfig_StallPeriod(final int value)
438 {
439
440 int regValue = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
441 regValue &= ~kTimerConfig_StallPeriod_BitfieldMask;
442 regValue |= ((value >>> kTimerConfig_StallPeriod_FixedPointIntegerShift) << kTimerConfig_StallPeriod_BitfieldOffset) & kTimerConfig_StallPeriod_BitfieldMask;
443 NiFpga.writeU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], regValue, status);
444 }
445 public void writeTimerConfig_AverageSize(final int value)
446 {
447
448 int regValue = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
449 regValue &= ~kTimerConfig_AverageSize_BitfieldMask;
450 regValue |= ((value) << kTimerConfig_AverageSize_BitfieldOffset) & kTimerConfig_AverageSize_BitfieldMask;
451 NiFpga.writeU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], regValue, status);
452 }
453 public void writeTimerConfig_UpdateWhenEmpty(final boolean value)
454 {
455
456 int regValue = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
457 regValue &= ~kTimerConfig_UpdateWhenEmpty_BitfieldMask;
458 regValue |= (((value ? 1 : 0)) << kTimerConfig_UpdateWhenEmpty_BitfieldOffset) & kTimerConfig_UpdateWhenEmpty_BitfieldMask;
459 NiFpga.writeU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], regValue, status);
460 }
461 public int readTimerConfig()
462 {
463
464 int result = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
465 int regValue = result ;
466 return (int)(regValue);
467 }
468 public int readTimerConfig_StallPeriod()
469 {
470
471 int result = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
472 int regValue = result ;
473 int bitfieldValue = ((regValue & kTimerConfig_StallPeriod_BitfieldMask) >>> kTimerConfig_StallPeriod_BitfieldOffset) << kTimerConfig_StallPeriod_FixedPointIntegerShift;
474 return (int)((bitfieldValue) & 0x01FFFFFF);
475 }
476 public byte readTimerConfig_AverageSize()
477 {
478
479 int result = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
480 int regValue = result ;
481 int bitfieldValue = ((regValue & kTimerConfig_AverageSize_BitfieldMask) >>> kTimerConfig_AverageSize_BitfieldOffset);
482 return (byte)((bitfieldValue) & 0x0000007F);
483 }
484 public boolean readTimerConfig_UpdateWhenEmpty()
485 {
486
487 int result = NiFpga.readU32(m_DeviceHandle, kTimerConfig_Addresses[m_SystemIndex], status);
488 int regValue = result ;
489 int bitfieldValue = ((regValue & kTimerConfig_UpdateWhenEmpty_BitfieldMask) >>> kTimerConfig_UpdateWhenEmpty_BitfieldOffset);
490 return ((bitfieldValue) != 0 ? true : false);
491 }
492
493
494
495
496
497 }