001 // Copyright (c) National Instruments 2009. All Rights Reserved.
002 // Do Not Edit... this file is generated!
003
004 package edu.wpi.first.wpilibj.fpga;
005
006 import com.ni.rio.*;
007
008 public class tSPI extends tSystem
009 {
010
011 public tSPI()
012 {
013 super();
014
015 }
016
017 protected void finalize()
018 {
019 super.finalize();
020 }
021
022 public static final int kNumSystems = 1;
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038 //////////////////////////////////////////////////////////////////////////////////////////////////
039 // Accessors for Status
040 //////////////////////////////////////////////////////////////////////////////////////////////////
041 private static final int kStatus_ReceivedDataOverflow_BitfieldMask = 0x00000002;
042 private static final int kStatus_ReceivedDataOverflow_BitfieldOffset = 1;
043 private static final int kStatus_Idle_BitfieldMask = 0x00000001;
044 private static final int kStatus_Idle_BitfieldOffset = 0;
045 private static final int kSPI_Status_Address = 0x8440;
046
047 public static int readStatus()
048 {
049
050 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Status_Address, status);
051 int regValue = result ;
052 return (int)(regValue);
053 }
054 public static boolean readStatus_ReceivedDataOverflow()
055 {
056
057 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Status_Address, status);
058 int regValue = result ;
059 int bitfieldValue = ((regValue & kStatus_ReceivedDataOverflow_BitfieldMask) >>> kStatus_ReceivedDataOverflow_BitfieldOffset);
060 return ((bitfieldValue) != 0 ? true : false);
061 }
062 public static boolean readStatus_Idle()
063 {
064
065 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Status_Address, status);
066 int regValue = result ;
067 int bitfieldValue = ((regValue & kStatus_Idle_BitfieldMask) >>> kStatus_Idle_BitfieldOffset);
068 return ((bitfieldValue) != 0 ? true : false);
069 }
070
071 //////////////////////////////////////////////////////////////////////////////////////////////////
072 // Accessors for ReceivedData
073 //////////////////////////////////////////////////////////////////////////////////////////////////
074 private static final int kSPI_ReceivedData_Address = 0x8434;
075
076 public static long readReceivedData()
077 {
078
079 return (long)((NiFpga.readU32(m_DeviceHandle, kSPI_ReceivedData_Address, status)) & 0xFFFFFFFFl);
080 }
081
082 //////////////////////////////////////////////////////////////////////////////////////////////////
083 // Accessors for DataToLoad
084 //////////////////////////////////////////////////////////////////////////////////////////////////
085 private static final int kSPI_DataToLoad_Address = 0x8428;
086
087 public static void writeDataToLoad(final long value)
088 {
089
090 NiFpga.writeU32(m_DeviceHandle, kSPI_DataToLoad_Address, (int)(value), status);
091 }
092 public static long readDataToLoad()
093 {
094
095 return (long)((NiFpga.readU32(m_DeviceHandle, kSPI_DataToLoad_Address, status)) & 0xFFFFFFFFl);
096 }
097
098 //////////////////////////////////////////////////////////////////////////////////////////////////
099 // Accessors for Config
100 //////////////////////////////////////////////////////////////////////////////////////////////////
101 private static final int kConfig_BusBitWidth_BitfieldMask = 0x007F8000;
102 private static final int kConfig_BusBitWidth_BitfieldOffset = 15;
103 private static final int kConfig_ClockHalfPeriodDelay_BitfieldMask = 0x00007F80;
104 private static final int kConfig_ClockHalfPeriodDelay_BitfieldOffset = 7;
105 private static final int kConfig_MSBfirst_BitfieldMask = 0x00000040;
106 private static final int kConfig_MSBfirst_BitfieldOffset = 6;
107 private static final int kConfig_DataOnFalling_BitfieldMask = 0x00000020;
108 private static final int kConfig_DataOnFalling_BitfieldOffset = 5;
109 private static final int kConfig_LatchFirst_BitfieldMask = 0x00000010;
110 private static final int kConfig_LatchFirst_BitfieldOffset = 4;
111 private static final int kConfig_LatchLast_BitfieldMask = 0x00000008;
112 private static final int kConfig_LatchLast_BitfieldOffset = 3;
113 private static final int kConfig_FramePolarity_BitfieldMask = 0x00000004;
114 private static final int kConfig_FramePolarity_BitfieldOffset = 2;
115 private static final int kConfig_WriteOnly_BitfieldMask = 0x00000002;
116 private static final int kConfig_WriteOnly_BitfieldOffset = 1;
117 private static final int kConfig_ClockPolarity_BitfieldMask = 0x00000001;
118 private static final int kConfig_ClockPolarity_BitfieldOffset = 0;
119 private static final int kSPI_Config_Address = 0x8418;
120
121 public static void writeConfig(final int value)
122 {
123
124 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, value, status);
125 }
126 public static void writeConfig_BusBitWidth(final int value)
127 {
128
129 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
130 regValue &= ~kConfig_BusBitWidth_BitfieldMask;
131 regValue |= ((value) << kConfig_BusBitWidth_BitfieldOffset) & kConfig_BusBitWidth_BitfieldMask;
132 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
133 }
134 public static void writeConfig_ClockHalfPeriodDelay(final int value)
135 {
136
137 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
138 regValue &= ~kConfig_ClockHalfPeriodDelay_BitfieldMask;
139 regValue |= ((value) << kConfig_ClockHalfPeriodDelay_BitfieldOffset) & kConfig_ClockHalfPeriodDelay_BitfieldMask;
140 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
141 }
142 public static void writeConfig_MSBfirst(final boolean value)
143 {
144
145 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
146 regValue &= ~kConfig_MSBfirst_BitfieldMask;
147 regValue |= (((value ? 1 : 0)) << kConfig_MSBfirst_BitfieldOffset) & kConfig_MSBfirst_BitfieldMask;
148 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
149 }
150 public static void writeConfig_DataOnFalling(final boolean value)
151 {
152
153 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
154 regValue &= ~kConfig_DataOnFalling_BitfieldMask;
155 regValue |= (((value ? 1 : 0)) << kConfig_DataOnFalling_BitfieldOffset) & kConfig_DataOnFalling_BitfieldMask;
156 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
157 }
158 public static void writeConfig_LatchFirst(final boolean value)
159 {
160
161 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
162 regValue &= ~kConfig_LatchFirst_BitfieldMask;
163 regValue |= (((value ? 1 : 0)) << kConfig_LatchFirst_BitfieldOffset) & kConfig_LatchFirst_BitfieldMask;
164 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
165 }
166 public static void writeConfig_LatchLast(final boolean value)
167 {
168
169 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
170 regValue &= ~kConfig_LatchLast_BitfieldMask;
171 regValue |= (((value ? 1 : 0)) << kConfig_LatchLast_BitfieldOffset) & kConfig_LatchLast_BitfieldMask;
172 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
173 }
174 public static void writeConfig_FramePolarity(final boolean value)
175 {
176
177 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
178 regValue &= ~kConfig_FramePolarity_BitfieldMask;
179 regValue |= (((value ? 1 : 0)) << kConfig_FramePolarity_BitfieldOffset) & kConfig_FramePolarity_BitfieldMask;
180 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
181 }
182 public static void writeConfig_WriteOnly(final boolean value)
183 {
184
185 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
186 regValue &= ~kConfig_WriteOnly_BitfieldMask;
187 regValue |= (((value ? 1 : 0)) << kConfig_WriteOnly_BitfieldOffset) & kConfig_WriteOnly_BitfieldMask;
188 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
189 }
190 public static void writeConfig_ClockPolarity(final boolean value)
191 {
192
193 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
194 regValue &= ~kConfig_ClockPolarity_BitfieldMask;
195 regValue |= (((value ? 1 : 0)) << kConfig_ClockPolarity_BitfieldOffset) & kConfig_ClockPolarity_BitfieldMask;
196 NiFpga.writeU32(m_DeviceHandle, kSPI_Config_Address, regValue, status);
197 }
198 public static int readConfig()
199 {
200
201 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
202 int regValue = result ;
203 return (int)(regValue);
204 }
205 public static short readConfig_BusBitWidth()
206 {
207
208 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
209 int regValue = result ;
210 int bitfieldValue = ((regValue & kConfig_BusBitWidth_BitfieldMask) >>> kConfig_BusBitWidth_BitfieldOffset);
211 return (short)((bitfieldValue) & 0x000000FF);
212 }
213 public static short readConfig_ClockHalfPeriodDelay()
214 {
215
216 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
217 int regValue = result ;
218 int bitfieldValue = ((regValue & kConfig_ClockHalfPeriodDelay_BitfieldMask) >>> kConfig_ClockHalfPeriodDelay_BitfieldOffset);
219 return (short)((bitfieldValue) & 0x000000FF);
220 }
221 public static boolean readConfig_MSBfirst()
222 {
223
224 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
225 int regValue = result ;
226 int bitfieldValue = ((regValue & kConfig_MSBfirst_BitfieldMask) >>> kConfig_MSBfirst_BitfieldOffset);
227 return ((bitfieldValue) != 0 ? true : false);
228 }
229 public static boolean readConfig_DataOnFalling()
230 {
231
232 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
233 int regValue = result ;
234 int bitfieldValue = ((regValue & kConfig_DataOnFalling_BitfieldMask) >>> kConfig_DataOnFalling_BitfieldOffset);
235 return ((bitfieldValue) != 0 ? true : false);
236 }
237 public static boolean readConfig_LatchFirst()
238 {
239
240 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
241 int regValue = result ;
242 int bitfieldValue = ((regValue & kConfig_LatchFirst_BitfieldMask) >>> kConfig_LatchFirst_BitfieldOffset);
243 return ((bitfieldValue) != 0 ? true : false);
244 }
245 public static boolean readConfig_LatchLast()
246 {
247
248 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
249 int regValue = result ;
250 int bitfieldValue = ((regValue & kConfig_LatchLast_BitfieldMask) >>> kConfig_LatchLast_BitfieldOffset);
251 return ((bitfieldValue) != 0 ? true : false);
252 }
253 public static boolean readConfig_FramePolarity()
254 {
255
256 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
257 int regValue = result ;
258 int bitfieldValue = ((regValue & kConfig_FramePolarity_BitfieldMask) >>> kConfig_FramePolarity_BitfieldOffset);
259 return ((bitfieldValue) != 0 ? true : false);
260 }
261 public static boolean readConfig_WriteOnly()
262 {
263
264 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
265 int regValue = result ;
266 int bitfieldValue = ((regValue & kConfig_WriteOnly_BitfieldMask) >>> kConfig_WriteOnly_BitfieldOffset);
267 return ((bitfieldValue) != 0 ? true : false);
268 }
269 public static boolean readConfig_ClockPolarity()
270 {
271
272 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Config_Address, status);
273 int regValue = result ;
274 int bitfieldValue = ((regValue & kConfig_ClockPolarity_BitfieldMask) >>> kConfig_ClockPolarity_BitfieldOffset);
275 return ((bitfieldValue) != 0 ? true : false);
276 }
277
278 //////////////////////////////////////////////////////////////////////////////////////////////////
279 // Accessors for ClearReceivedData
280 //////////////////////////////////////////////////////////////////////////////////////////////////
281 private static final int kSPI_ClearReceivedData_Address = 0x843C;
282
283 public static void strobeClearReceivedData()
284 {
285
286 NiFpga.writeU32(m_DeviceHandle, kSPI_ClearReceivedData_Address, 1, status);
287 }
288
289 //////////////////////////////////////////////////////////////////////////////////////////////////
290 // Accessors for ReceivedElements
291 //////////////////////////////////////////////////////////////////////////////////////////////////
292 private static final int kSPI_ReceivedElements_Address = 0x8438;
293
294 public static short readReceivedElements()
295 {
296
297 return (short)((NiFpga.readU32(m_DeviceHandle, kSPI_ReceivedElements_Address, status)) & 0x000001FF);
298 }
299
300 //////////////////////////////////////////////////////////////////////////////////////////////////
301 // Accessors for Load
302 //////////////////////////////////////////////////////////////////////////////////////////////////
303 private static final int kSPI_Load_Address = 0x8424;
304
305 public static void strobeLoad()
306 {
307
308 NiFpga.writeU32(m_DeviceHandle, kSPI_Load_Address, 1, status);
309 }
310
311 //////////////////////////////////////////////////////////////////////////////////////////////////
312 // Accessors for Reset
313 //////////////////////////////////////////////////////////////////////////////////////////////////
314 private static final int kSPI_Reset_Address = 0x8420;
315
316 public static void strobeReset()
317 {
318
319 NiFpga.writeU32(m_DeviceHandle, kSPI_Reset_Address, 1, status);
320 }
321
322 //////////////////////////////////////////////////////////////////////////////////////////////////
323 // Accessors for Channels
324 //////////////////////////////////////////////////////////////////////////////////////////////////
325 private static final int kChannels_SCLK_Channel_BitfieldMask = 0x000F0000;
326 private static final int kChannels_SCLK_Channel_BitfieldOffset = 16;
327 private static final int kChannels_SCLK_Module_BitfieldMask = 0x00008000;
328 private static final int kChannels_SCLK_Module_BitfieldOffset = 15;
329 private static final int kChannels_MOSI_Channel_BitfieldMask = 0x00007800;
330 private static final int kChannels_MOSI_Channel_BitfieldOffset = 11;
331 private static final int kChannels_MOSI_Module_BitfieldMask = 0x00000400;
332 private static final int kChannels_MOSI_Module_BitfieldOffset = 10;
333 private static final int kChannels_MISO_Channel_BitfieldMask = 0x000003C0;
334 private static final int kChannels_MISO_Channel_BitfieldOffset = 6;
335 private static final int kChannels_MISO_Module_BitfieldMask = 0x00000020;
336 private static final int kChannels_MISO_Module_BitfieldOffset = 5;
337 private static final int kChannels_SS_Channel_BitfieldMask = 0x0000001E;
338 private static final int kChannels_SS_Channel_BitfieldOffset = 1;
339 private static final int kChannels_SS_Module_BitfieldMask = 0x00000001;
340 private static final int kChannels_SS_Module_BitfieldOffset = 0;
341 private static final int kSPI_Channels_Address = 0x841C;
342
343 public static void writeChannels(final int value)
344 {
345
346 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, value, status);
347 }
348 public static void writeChannels_SCLK_Channel(final int value)
349 {
350
351 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
352 regValue &= ~kChannels_SCLK_Channel_BitfieldMask;
353 regValue |= ((value) << kChannels_SCLK_Channel_BitfieldOffset) & kChannels_SCLK_Channel_BitfieldMask;
354 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, regValue, status);
355 }
356 public static void writeChannels_SCLK_Module(final int value)
357 {
358
359 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
360 regValue &= ~kChannels_SCLK_Module_BitfieldMask;
361 regValue |= ((value) << kChannels_SCLK_Module_BitfieldOffset) & kChannels_SCLK_Module_BitfieldMask;
362 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, regValue, status);
363 }
364 public static void writeChannels_MOSI_Channel(final int value)
365 {
366
367 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
368 regValue &= ~kChannels_MOSI_Channel_BitfieldMask;
369 regValue |= ((value) << kChannels_MOSI_Channel_BitfieldOffset) & kChannels_MOSI_Channel_BitfieldMask;
370 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, regValue, status);
371 }
372 public static void writeChannels_MOSI_Module(final int value)
373 {
374
375 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
376 regValue &= ~kChannels_MOSI_Module_BitfieldMask;
377 regValue |= ((value) << kChannels_MOSI_Module_BitfieldOffset) & kChannels_MOSI_Module_BitfieldMask;
378 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, regValue, status);
379 }
380 public static void writeChannels_MISO_Channel(final int value)
381 {
382
383 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
384 regValue &= ~kChannels_MISO_Channel_BitfieldMask;
385 regValue |= ((value) << kChannels_MISO_Channel_BitfieldOffset) & kChannels_MISO_Channel_BitfieldMask;
386 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, regValue, status);
387 }
388 public static void writeChannels_MISO_Module(final int value)
389 {
390
391 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
392 regValue &= ~kChannels_MISO_Module_BitfieldMask;
393 regValue |= ((value) << kChannels_MISO_Module_BitfieldOffset) & kChannels_MISO_Module_BitfieldMask;
394 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, regValue, status);
395 }
396 public static void writeChannels_SS_Channel(final int value)
397 {
398
399 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
400 regValue &= ~kChannels_SS_Channel_BitfieldMask;
401 regValue |= ((value) << kChannels_SS_Channel_BitfieldOffset) & kChannels_SS_Channel_BitfieldMask;
402 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, regValue, status);
403 }
404 public static void writeChannels_SS_Module(final int value)
405 {
406
407 int regValue = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
408 regValue &= ~kChannels_SS_Module_BitfieldMask;
409 regValue |= ((value) << kChannels_SS_Module_BitfieldOffset) & kChannels_SS_Module_BitfieldMask;
410 NiFpga.writeU32(m_DeviceHandle, kSPI_Channels_Address, regValue, status);
411 }
412 public static int readChannels()
413 {
414
415 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
416 int regValue = result ;
417 return (int)(regValue);
418 }
419 public static byte readChannels_SCLK_Channel()
420 {
421
422 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
423 int regValue = result ;
424 int bitfieldValue = ((regValue & kChannels_SCLK_Channel_BitfieldMask) >>> kChannels_SCLK_Channel_BitfieldOffset);
425 return (byte)((bitfieldValue) & 0x0000000F);
426 }
427 public static byte readChannels_SCLK_Module()
428 {
429
430 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
431 int regValue = result ;
432 int bitfieldValue = ((regValue & kChannels_SCLK_Module_BitfieldMask) >>> kChannels_SCLK_Module_BitfieldOffset);
433 return (byte)((bitfieldValue) & 0x00000001);
434 }
435 public static byte readChannels_MOSI_Channel()
436 {
437
438 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
439 int regValue = result ;
440 int bitfieldValue = ((regValue & kChannels_MOSI_Channel_BitfieldMask) >>> kChannels_MOSI_Channel_BitfieldOffset);
441 return (byte)((bitfieldValue) & 0x0000000F);
442 }
443 public static byte readChannels_MOSI_Module()
444 {
445
446 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
447 int regValue = result ;
448 int bitfieldValue = ((regValue & kChannels_MOSI_Module_BitfieldMask) >>> kChannels_MOSI_Module_BitfieldOffset);
449 return (byte)((bitfieldValue) & 0x00000001);
450 }
451 public static byte readChannels_MISO_Channel()
452 {
453
454 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
455 int regValue = result ;
456 int bitfieldValue = ((regValue & kChannels_MISO_Channel_BitfieldMask) >>> kChannels_MISO_Channel_BitfieldOffset);
457 return (byte)((bitfieldValue) & 0x0000000F);
458 }
459 public static byte readChannels_MISO_Module()
460 {
461
462 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
463 int regValue = result ;
464 int bitfieldValue = ((regValue & kChannels_MISO_Module_BitfieldMask) >>> kChannels_MISO_Module_BitfieldOffset);
465 return (byte)((bitfieldValue) & 0x00000001);
466 }
467 public static byte readChannels_SS_Channel()
468 {
469
470 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
471 int regValue = result ;
472 int bitfieldValue = ((regValue & kChannels_SS_Channel_BitfieldMask) >>> kChannels_SS_Channel_BitfieldOffset);
473 return (byte)((bitfieldValue) & 0x0000000F);
474 }
475 public static byte readChannels_SS_Module()
476 {
477
478 int result = NiFpga.readU32(m_DeviceHandle, kSPI_Channels_Address, status);
479 int regValue = result ;
480 int bitfieldValue = ((regValue & kChannels_SS_Module_BitfieldMask) >>> kChannels_SS_Module_BitfieldOffset);
481 return (byte)((bitfieldValue) & 0x00000001);
482 }
483
484 //////////////////////////////////////////////////////////////////////////////////////////////////
485 // Accessors for AvailableToLoad
486 //////////////////////////////////////////////////////////////////////////////////////////////////
487 private static final int kSPI_AvailableToLoad_Address = 0x842C;
488
489 public static short readAvailableToLoad()
490 {
491
492 return (short)((NiFpga.readU32(m_DeviceHandle, kSPI_AvailableToLoad_Address, status)) & 0x000001FF);
493 }
494
495 //////////////////////////////////////////////////////////////////////////////////////////////////
496 // Accessors for ReadReceivedData
497 //////////////////////////////////////////////////////////////////////////////////////////////////
498 private static final int kSPI_ReadReceivedData_Address = 0x8430;
499
500 public static void strobeReadReceivedData()
501 {
502
503 NiFpga.writeU32(m_DeviceHandle, kSPI_ReadReceivedData_Address, 1, status);
504 }
505
506
507
508
509 }